Electronics Weekly

IMEC develops VLIW, coarse-grained DSP

IMEC has developed a DSP architecture template combining a very long instruction word (VLIW) processor and coarse-grained array, and a prototype C compiler which enables easy programming of the ...
EDN

IMEC Claims Coarse-Grain Processor Breakthrough

To address mobile terminal requirement of the future, independent Belgium-based research firm IMEC has created a coarse-grain processor — Architecture for Dynamically Reconfigurable Embedded System ...
Design-Reuse

VLSI Based On Two-Dimensional Reconfigurable Array Of Processor Elements And Theirs Implementation For Numerical Algorithms In Real-Time Systems

High-speed data processing based upon special-purpose processors is one of the basic directions in the development of computer systems for real-time systems. Reconfigurable processor arrays containing ...
Design-Reuse

3+ ways to design reconfigurable algorithm accelerator in IP block

Three ways to design a reconfigurable algorithm accelerator are shown. It is also presented that the problem field makes it possible to make such a simplifications that any parallel topology can ...