MicroCloud Hologram Inc. Launches FPGA-Based High-Performance Surface Code Quantum Simulation Platform

MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, launched a simulator that fully leverages the unique advantages of FPGA (Field-Programmable Gate ...
Morningstar

MicroCloud Hologram Inc. FPGA-Based High-Performance Surface Code Quantum Simulation Platform: Efficient Error Correction Algorithm Validation under Rotated Layout

SHENZHEN, China, Feb. 25, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a technology service provider, has developed a surface code quantum simulator based ...
Seeking Alpha

WiMi Develops a Hybrid CPU-FPGA Quantum AI Simulator

BEIJING, Jan. 14, 2025 /PRNewswire/ -- WiMi Hologram Cloud Inc. (WIMI) ("WiMi" or the "Company"), a leading global Hologram Augmented Reality ("AR") Technology provider, today announced the ...
manilatimes

MicroCloud Hologram Inc. Proposes Quantum AI Simulator Adopting Hybrid CPU-FPGA Method, Achieving Efficient Image Classification Simulation Through Heterogeneous Computing

SHENZHEN, China, Feb. 26, 2026 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO” or the "Company"), a technology service provider, proposed a quantum AI simulator that adopts a ...
Nasdaq

Lattice Diamond Software Tool Delivers New Enhancements for FPGA Design, Simulation, and Verification

HILLSBORO, Ore.--(BUSINESS WIRE)-- Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced availability of the latest version of its popular FPGA design ...
Embedded

What’s involved in simulation of a complex SoC FPGA like Versal ACAP?

AMD’s Versal adaptive compute acceleration platform (ACAP) is a system-on-chip (SoC) device architecture (see figure 1) includes three groups of engines – scalar, adaptable, and intelligent – plus ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...