Semiconductor Engineering

Multi-Die Assemblies Require More Detailed Test Plan Earlier

Understanding connectivity issues and interactions are only part of the problem; ECOs can cause unexpected problems in other ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
Electronic Design

Penny-A-Secnd SoC DFT Tester Saves Time

At $399,000, the 93000 SoC (system-on-a-chip) DFT (design for test) series promises users a one-cent-per-second cost of test. As such, this version of the Agilent Technologies 93000 SoC platform would ...
Electronics Weekly

Network software for Tessent TestKompress simplifies DFT flow

To meet the increasing size of ICs, required to accommodate the integration of billions of transistors in order to deliver the performance required for tasks such as AI and autonomous vehicles, Mentor ...